For the past month and a half or so, I've been developing an implementation of an error-correcting code1 for a satellite communication system, to be loaded into an FPGA2. The architecture has been a lot of fun to develop because it's challenging, high-level thinking. The specs were slightly less fun to write, because they require getting into the nitty-gritty a bit more, but doing this shed considerable light on how to improve the architecture. The VHDL3 was interesting to write, because I was learning how to do it, and because it's fulfilling to see the architecture become real.
Now, it's getting down to the last stages of packaging, debugging and optimization. Today's accomplishment was redesigning a control module completely to reduce the complexity of operations performed in a single clock cycle, thus decreasing the real time required between clock pulses and increasing the maximum clock speed. I suspect that there will be a LOT of this kind of thing to do, even once the core (what software folks would call "code") is "working," i.e. giving the right outputs for given inputs. It's interesting, and I'm learning things, but I don't want to do it until I retire.
I bore easily. Originally, the implementation of this (once the architecture was settled) was supposed to be done at least partly by someone else, but that keeps not happening because he's busy with other things, and maybe because I seem to be able to keep the schedule on track without him. Hopefully, I'll be done before I get terminally fed up with this... the race is on!
1: A trick used to deal with the fact that there's noise on channels by sending redundant information and analyzing the received signal to infer the original input even if reception was imperfect. For example, if a radio operator says "yes" and you lose a syllable, you get "xxx", which could be anything. If, however, the operator says "affirmative" and you lose a syllable, you get "afxxxmative", which still conveys the meaning. Only this is with digital bits, has to happen really fast, and has a relatively small proportion of redundant information to work with.
2: Field Programmable Gate Array. A microchip which can be configured to behave like a custom-built microchip. It can do lots of things in parallel, and generally is configured to perform a very specific task extremely fast by doing many parts of it at once. A standard microprocessor (like the one in the computer on which you're reading this) does one thing at a time, but can do this about 3 billion times per second; this chip will be doing between 100 and 1000 things at once about 100 million times per second, for a net speed of 10 to 100 billion operations per second!
3: VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit. A language in which the behaviour and structure of circuits like this can be described. It looks and smells a lot like a programming language, but is a bit different because of its need to handle physical parameters and delay times of devices, and truly concurrent operations.